The cell of a semiconductor memory such as a dynamic random access memory (DRAM) device is generally created comprising one single Metal-Oxide-Semiconductor Field-Effect-Transistor (MOS-FET) as a switching device connected with a capacitor as a digital data storage device. A capacitor known as a metal-insulator-metal (MIM) structure possesses a low-interfacial reaction specificity to enhance its performance. The MIM capacitor has therefore become an important topic of research for the memory technology in the future. As the DRAM device needs ultra-high integrity, cell areas are reduced, and thus many studies for increasing the capacitance of a MIM capacitor are being developed. There are various ways of increasing the capacitance such as forming a crown-shaped capacitor structure, whereby a surface area of a dielectric layer is increased. However, the conventional process needs to form a thick insulator layer in openings to increase the vertical dimension of the crown-shaped capacitor structure, resulting in a high aspect ratio of bit line contact holes for capacitor-over-bit line (COB) designs. The formation of the thick insulator layer increases process complexity and cost, and causes difficulties in anisotropically etching bit line contact holes with deep and narrow designs.
What is needed in the art, therefore, is a novel approach to increase capacitance and maintaining the capacitor height simultaneously to minimize an impact on the bit line contact aspect ratio.